Verification Engineer - SoC / SystemVerilog / ASIC

Verification Engineer - SoC / SystemVerilog / ASIC

We are partnered with a fast growing semiconductor start-up in the Netherlands working on cutting-edge secure CPU technologies. They are looking to expand their team with an ASIC Verification Engineer to play a critical role in verifying complex SoC architectures, ensuring they meet rigorous functional, performance, and compliance standards.

This is a hands-on engineering role with significant influence over process, quality, and performance outcomes across the full verification lifecycle.

This is a permanent opportunity based in Amsterdam, the Netherlands.

Key Responsibilities for this Verification Engineer position:

• Design, develop, and maintain UVM-based verification environments for complex digital and SoC designs
• Create and execute detailed test plans based on functional specs
• Build robust test benches to validate functionality, performance, and standards compliance
• Debug issues in collaboration with design and architecture teams
• Drive best practices and improvements in verification processes and methodology
• Participate in architecture and design reviews with a verification-focused perspective
• Align verification activities with broader project goals, including emulation and HW/SW co-design

Key Requirements:

• 5+ years of experience in ASIC verification
• Strong knowledge of digital logic design, processor-based system verification, and SoC architecture
• Proficiency in SystemVerilog, UVM, and scripting languages (Tcl, Python, Perl)
• Familiarity with standard interfaces: PCIe, DDR, UCIe, Ethernet
• Experience with C/C++, formal verification, and emulation platforms
• Bachelor's degree in Electrical or Computer Engineering (Master's preferred)
• Exposure to HW/SW co-simulation (e.g., QEMU) is a plus

If you are interested in this Verification Engineer position, please send a copy of your CV to

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