Senior RISC-V RTL Design Engineer (Microarchitecture)

SiFive is hiring a CPU Microarchitecture/RTL design engineer to join a team delivering industry leading CPU cores based on the open source RISC V architecture. You will design features, extend ISA, and integrate content into Chisel/FIRRTL while coordinating with verification and physical teams.

You will contribute to documentation, improve testbenches, and drive performance exploration to meet aggressive goals in a fast paced environment.