Senior Physical Design Engineer

A pioneering company in AI and semiconductor solutions, is seeking a highly skilled Senior Physical Design Engineer to contribute to the development of advanced multi-core in-memory compute SoCs. This role offers the chance to work on high-performance ASICs in a fast-growing, innovation-driven environment with a global team.

Key responsibilities

• Lead full-chip physical design tasks including synthesis, floorplanning, placement, routing, extraction, and verification
• Develop strategies for timing closure, clock-tree synthesis, and signal integrity
• Integrate IP blocks such as memories, I/Os, embedded cores, and interconnects
• Collaborate with cross-functional teams to troubleshoot design or tool-related challenges
• Contribute to automation and flow development using Python, Tcl, or Bash scripting
• Provide technical guidance and mentorship to junior engineers.

Desired experience

• Extensive knowledge of ASIC physical design from RTL to GDSII
• Hands-on experience with EDA tools such as Innovus, Genus, Design Compiler, ICC2, Primetime, StarRC, Redhawk, or equivalents
• Expertise in clocking strategies, CTS, and top-level integration
• Strong scripting skills and experience improving design flows
• Excellent problem-solving abilities and debugging skills
• Fluent in English, both written and spoken

Additional advantages

• Exposure to chip-package-board co-simulation and advanced packaging techniques
• Experience working with EDA vendors to resolve tool or methodology issues
• Knowledge of semiconductor device physics or multi-domain design considerations

This is a high-impact role where the Senior Physical Design Engineer will play a pivotal part in delivering next-generation AI and compute solutions with a world-class global team.