Senior FPGA Architect: High-Speed RTL & Compute

Quantum Dice, based in Oxford, UK, seeks a senior FPGA engineer to translate probabilistic models into high-performance RTL and integrate with analogue front ends.

You will design from scratch in VHDL/Verilog, work with PS/PL architectures, and ensure timing closure across clock domains. Strong HDL, lab debug, and FPGA toolchain experience are essential.

This role offers collaboration with academia and industry, tackling real-world probabilistic computing and ASIC-tapeout preparation.