Senior Digital Verification Architect - Chiplet MDV Lead

Cadence Design Systems in Edinburgh is seeking a Digital Electronics Principal Verification Engineer to lead verification efforts for advanced Chiplet designs. You will develop verification and emulation environments, UVM-SV scoreboards, functional coverage, and SystemVerilog assertions to ensure high-quality silicon.

The role requires 10+ years in microelectronics/EDA, strong Verilog RTL experience, and excellent English communication.