Senior DFT Architect for ASIC/SoC & ATPG

Analog Devices is seeking a senior DFT engineer to lead DFT specifications and implementation across ASIC/SoC projects. You will apply advanced DFT techniques, leverage Tessent and Cadence/Synopsys tools, and drive high-coverage ATPG while mentoring junior teammates.

You will collaborate with design and verification teams to optimize scan architectures, test time, and silicon bring-up, contributing to robust, scalable DFT flows across product lines.