Senior Design Verification Engineer

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This is a superb opportunity to join one of the hottest names in the industry! A chance to build a technology that transforms the future of humanity. A chance to work on products that have set the standard in made-for-AI compute hardware and software. A chance to be part of the AI revolution!

I am looking for experienced Verification Engineers to join a world class silicon engineering team, joining a company who bring large and ongoing investment from one of the world's leading backers of innovative AI companies! SW Verification experience with Python, C/C++ is welcome alongside the traditional UVM based Verification.

Responsibilities and duties

• Verification activities within the verification team
• Verification planning, specification and closure of functional coverage
• Providing feedback to architects
• Test generation and failure diagnosis/triage
• Contributing to shared verification infrastructure

Candidate profile

• 10+ years of Verification experience
• Verification experience in relevant industry
• Proven leadership and planning skills
• Ability to work across teams and programming languages to find root causes of deep and complex issues
• Experience of the verification process applied in CPU and/or ASIC environments
• System Verilog, Python, C++, Linux
• UVM
• SVA
• LLVM, GCC
• SGE or other DRMS
• XML and XPath/XSLT

In addition to a competitive salary, you can expect flexible working, a generous annual leave policy, private medical insurance and health cash plan, a dental plan, pension (matched up to 5%), life assurance and income protection.

7710 N FM 620,Bldg. 13-d, Austin.Texas 78726

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