RTL Engineers (Risc-V)

We are seeking experienced RTL Design Engineers with strong RICS-V knowledge to join a dynamic and innovative team working at the forefront of processor and SoC design. The ideal candidate is passionate about digital design and thrives in a collaborative environment that values innovation, autonomy, and technical excellence.

Key Responsibilities

• Design, implement, and verify RTL components using Verilog for complex digital systems.
• Collaborate closely with architecture, verification, and physical design teams to ensure seamless integration and high performance.
• Participate in design reviews, provide feedback, and drive best practices in RTL development.
• Write and maintain scripts to automate flows and enhance productivity.
• Contribute to performance optimization and power-efficiency initiatives across the design lifecycle.
• Support and mentor junior engineers, sharing expertise and fostering a culture of continuous improvement.

Requirements

• Bachelor's degree or higher in Computer Science, Electrical Engineering, or a related field.
• 8+ years of hands-on experience in RTL design and implementation.
• Proficient in Verilog HDL and capable of writing clean, efficient, and scalable code.
• Strong scripting skills (e.g., Python, Perl, Tcl, Shell) for automation and tool integration.
• Advanced English communication skills (minimum C1 level), both written and verbal.
• Solid understanding of digital design principles, including timing, clock domains, and low-power techniques.
• Experience with version control systems and industry-standard EDA tools.
• Experience with RISC-V architecture or other processor cores.
• Familiarity with SoC integration, system buses (e.g., AXI, AHB), and memory subsystems.
• Exposure to formal verification or emulation environments.

If you meet the requirements and are excited about this opportunity, we encourage you to apply today or email your CV to and become part of our growing team!