Principal CPU Microarchitect

A leading innovator in the CPU domain is seeking an experienced and talented Principal CPU Micro-architect to drive microarchitecture and modelling for their next generation OOO processor cores.

Responsibilities

• Define and specify microarchitectural features across pipeline stages - fetch/decode, OoO execution, LSU, prefetchers, branch prediction, and cache hierarchy
• Build and maintain cycle-accurate performance models to evaluate new features against mobile workloads
• Drive workload analysis combining cycle-accurate modelling with simpleperf, hardware counters, and trace-based methods to identify bottlenecks and quantify uplift opportunities
• Co-design ISA extensions with compiler and runtime teams, including ISA extensions, prefetch hints, and semantic acceleration primitives
• Author detailed microarchitecture specifications and partner with design teams on implementation trade-offs
• Mentor junior engineers and contribute to the team's technical direction across multiple parallel tracks (prefetch, semantic acceleration, AI4CPU)

Qualifications

• Strong CPU microarchitecture experience on OOO cores
• Deep working knowledge of at least one major area: branch prediction, prefetching, OoO execution, memory subsystem, or cache coherence
• Proven experience with cycle-accurate simulators (gem5 or proprietary equivalents)
• Strong workload analysis skills - performance counter methodology, top-down analysis, trace inspection
• Proficient in C++ and Python for modelling, analysis tooling, and automation
• Familiarity with ARMv8/v9, Intel x86_64 or RISC-V ISA at the microarchitectural level
• MSc or PhD in Computer Science, Electrical Engineering, or equivalent industry experience