Power Management DV Engineer - Early to Experienced

Apple Inc. is seeking a Design Verification Engineer in Swindon to enable bug-free silicon for mixed-signal designs.

You will craft verification plans, build test benches, and develop automated flows with SystemVerilog, UVM, and other verification tools across RTL and chip-level stages. The role requires strong knowledge of SystemVerilog/UVM, test bench development, and experience in coverage-driven verification.