MC Sub-System Verification Engineer IRC300820

We have an exciting opportunity for an experienced Senior Software Engineer to help drive innovation across a diverse product portfolio.
In this role, you will be at the heart of our operations, collaborating with a dynamic team to develop critical solutions for security, power management, and system on chip (SoC) functions. Your work will span key business units including IoT, Mobile, Auto, XR, and Compute, providing you with a unique opportunity to influence technology that powers a wide range of cutting edge products.

Requirements

• Bachelor's degree in Science, Engineering, or a related field.
• 5 8 years Software Engineering experience
• 3+ years of ASIC design verification experience, preferably with UVM based.
• ISA Verification: Familiarity with ARM or RISC V ISA verification.
• Formal Verification Tools: Experience using formal verification tools like Jasper or VC_Formal is a plus.
• Microcontroller/Sub System Knowledge: Understanding of processor/microcontroller sub systems is advantageous.
• AMBA Bus Protocols: Familiarity with AMBA bus protocols is desirable.
• Gate Level Simulation and Power Extraction: Experience with gate level simulation debug and power extraction tools is beneficial.
• Power Aware Verification: Knowledge of power aware verification methodologies.
• Coverage Driven Verification: Proficiency in constrained random verification environments and coverage driven methodologies.
• System Verilog Assertions: Familiarity with System Verilog assertions.
• Debugging Skills: Ability to debug test failures and report verification results to achieve expected code/functional/line coverage goals.
• RTL Simulation Tools: Extensive usage of RTL simulation tools.
• Scripting Proficiency: Skills in UVM, System Verilog, and Perl/Python shell scripting.
• C/C++ Familiarity: Basic familiarity with C/C++.

Job responsibilities

• Play a vital part in advancing technological excellence.
• Deploy industry leading verification methodologies such as Universal Verification Methodology (UVM) and Formal Verification.
• Create testbenches and verification components, including Universal Verification Components (UVCs), C models, and reusable vertical/horizontal verification environments.
• Ensure comprehensive coverage and collaborate with design teams to address coverage gaps.
• Work closely with design, SoC, and validation teams to solve problems at various levels.
• Assist in integrating design into higher level subsystems, including test planning, test vector delivery, and test vector debugging.

Benefits

Comprehensive health and wellness plan, private healthcare (clinical and mental wellbeing), discounted gym memberships, a competitive pension scheme, recognition schemes through bonus/reward initiatives, and annual volunteering days.

Equal Opportunity

We are an equal opportunities employer. It is our policy to promote an environment free from discrimination, harassment and victimisation.