AI-Driven ASIC Mid-End Engineer - Synthesis & Automation

Synopsys seeks an EDA flow and Logic Synthesis Engineer (Staff Engineer) to join our mid-end team and own ASIC design-to-implementation flows. You will develop and refine synthesis, DFT, and power analysis processes, while ensuring clean RTL-to-physical-design handoffs.

You will build Tcl-based automation, dashboards, and project infrastructure, applying AI to triage flow logs, summarize QoR trends, and draft improved scripts.