Verification Engineer

Posted 18 minutes 15 seconds ago by Chipright

Permanent
Part Time
Other
Not Specified, United Kingdom
Job Description
Experience Required
  • Extensive experience of designing and implementing verification environments for complex RTL designs.
  • Well-versed in the use of class based hardware verification languages e.g. SystemVerilog or Specman 'e.'
  • Detail Knowledge of Verification methodologies such as UVM.
  • In-Depth understanding of end-to-end verification processes, from test plan creation through to verification closure.
  • Understanding of constrained random stimulus, the goals and general usefulness of different types of coverage in hardware, as well as checking methodologies and behavioural functional models.
  • Ability to quickly understand and apply complex specification detail.
  • Familiarity with Mentor Questasim simulator required.
  • Synopsys VCS & Cadence Incisive nice to have.
  • The system that would be worked by the contractor would be able to run on these simulators.
  • Familiarity with GIT.
  • Scope of the project: UVM based verification of a complex multi unit System IP product.