Staff Digital Design Verification Engineer RTL, UVM, Formal

A leading Multinational Semiconductor Telecom Company is seeking a Staff Digital Design Verification Engineer to join its Sensor Team in Cork City, Ireland. This role requires onsite presence five days a week and involves deploying advanced verification methodologies, developing testbenches, and verifying algorithms for ASIC tapeout. Candidates should have a Bachelor's degree and over 6 years of ASIC design verification experience with strong skills in UVM and SystemVerilog. The position offers a dynamic work environment with collaboration across teams.