SoC Physical Design Lead for Full-Chip Tape-Out

Deel is seeking a Principal Engineer to lead ASIC/SoC physical design from architecture to tape-out in Greater London. You will drive floorplanning, power planning, clocking, place-and-route, timing closure and signoff while coordinating with Architecture, RTL, Verification, DFT, STA, Package and Silicon Validation teams.

The role requires a hands-on leader with strong collaboration skills and a track record of successful full-chip tape-outs, including integration of IPs across vendors and