Senior Verification Architect for Mixed-Signal ASICs

Renesas Electronics Corporation is seeking a Staff Design Verification Engineer to develop and execute verification plans for complex mixed-signal ASIC designs. The role involves creating and maintaining testbenches, writing test cases, and collaborating with design engineers to ensure verification requirements are met.

The ideal candidate will have 10+ years of experience in design verification, strong skills in SystemVerilog and UVM, and experience with scripting for automation. Renesas is committed to diversity and creating an inclusive workplace.