Senior RTL Engineer - CPU Frontend (RISC-V)

SiFive, Inc. in Cambridge, UK seeks a Senior RTL Design Engineer to architect and implement new features for RISC-V CPU frontends.

You will integrate content into the Chisel/FIRRTL framework and support automatic configuration, docs, and robust verification. You will verify designs in sandbox environments, collaborate with physical implementation to meet frequency and power goals, and work with performance modeling for optimization.