Senior Packaging Design Engineer London, UK, Bristol, UK and Austin, TX

AI is growing faster than any technology in history and the explosion in demand has created a massive infrastructure gap; we can no longer build chips or power stations fast enough to keep up. The industry is still leaning on a ten-year-old hardware blueprint that has reached its limit. A new paradigm that is faster and more efficient will be the biggest economic opportunity of the next century and create the most important company of the next decade. The OLIX Decode Accelerator 1 (DX-1) is the first accelerator architected specifically for decode. Rack-scale co-design of logic, data movement, packaging, optics and interconnect enables a step change in system level performance.

At OLIX, the performance of our technology depends not only on silicon design, but on how effectively that silicon is packaged, integrated, and scaled into products. As we move from early architecture and prototype development toward productisation, the Senior / Staff Packaging Engineer will play a critical role in defining and delivering the packaging solutions that enable our ASICs to become high-performance systems.

This is a hands on, high impact engineering role focused on front end package design, ASIC to substrate integration, and advanced 2.5D and 3D packaging. You will work across silicon, substrate, package, and board level interfaces to ensure package solutions meet performance, manufacturability, and integration requirements from concept through to production readiness.

You will lead packaging engineering across the full development flow, including package architecture, detailed design, layout, simulation, and product readiness. This includes defining package design methodologies, owning substrate design, delivering PI/SI simulations, and supporting substrate and PCB integration as needed. Working closely with the ASIC team, you will translate die requirements into package solutions that are electrically robust, manufacturable, and ready for system integration.

A key part of the role will be owning the end to end package design flow for next generation AI hardware, including package architecture, bump and substrate design, package layout, high speed and power delivery integration, PI/SI driven optimisation, and substrate/PCB co design.

Advanced Package Architecture & Design

Own package design activities for ASIC to substrate integration, including bump/pad mapping, substrate escape, interconnect strategy, package floorplanning, and stack up definition

Lead the development of 2.5D and 3D package architectures, including multi die integration, chiplet style interfaces, and heterogeneous integration approaches

Define package structures that meet electrical, thermal, mechanical, reliability, and manufacturability requirements

Translate silicon and system requirements into practical package design rules, routing constraints, and implementation strategies

Drive package technology selection based on performance, risk, manufacturability, cost, and scalability

Full Package Design Flow

Own or lead the full package design flow, from concept definition through detailed design, analysis, layout, verification, release, and manufacturing support

Develop and review package layouts including die placement, substrate routing, power/ground distribution, high speed interface breakout, and physical integration constraints

Own and execute PI/SI simulation activities to validate signal integrity, power delivery, and package performance, translating results directly into design improvements and sign off decisions

Support package to board co design, including substrate layout and PCB layout/interface definition where required

Ensure strong alignment between die, package, substrate, and board level implementation

Oversee package database management, design reviews, sign off, and release readiness

Tools, Methods & Implementation

Use package design tools such as Cadence Allegro X APD, or equivalent to develop and maintain advanced package and substrate layouts

Establish and improve package design libraries, templates, rules, and workflows to support efficient and repeatable development

Drive layout reviews, implementation checks, and sign off processes to ensure package integrity and compliance with technology and manufacturing constraints

Support tool flow development and integration across package, substrate, simulation, and PCB environments

Ensure robust design data handoff to substrate vendors, OSATs, and manufacturing partners

Cross Functional Engineering

Work closely with ASIC, mechanical, thermal, and systems engineers to optimise package performance and system integration

Collaborate with substrate vendors, OSATs, foundries, and external partners on stack ups, design rules, implementation feasibility, and manufacturing readiness

Lead packaging input into architecture reviews, risk assessments, and development planning

Ensure package design decisions support broader product requirements including manufacturability, reliability, serviceability, and scale

Act as the key interface between package design and adjacent engineering domains

Manufacturing & Productisation Support

Ensure package designs are aligned with assembly, qualification, reliability, and manufacturing requirements

Lead DFM/DFX activities for advanced package technologies and substrate implementations

Support prototype build, bring up, qualification, and early production with strong technical ownership of packaging related issues

Participate in root cause analysis and corrective action for packaging or integration issues identified during build, test, or reliability assessment

Review substrate deliverables, fabrication outputs, and manufacturing documentation for completeness and technical quality

Deep expertise in advanced semiconductor packaging for ASIC or other high performance products

Deep expertise in front end package design, including ASIC to substrate integration

Strong experience with 2.5D and/or 3D package architectures

Strong hands on capability with package design tools such as Cadence Allegro, Siemens Xpedition, or equivalent

Experience leading package development across layout, simulation, verification, and release

Strong hands on PI/SI simulation capability, including experience running package level signal integrity and power delivery analysis using tools such as Ansys SIwave, Cadence Sigrity, or equivalent

Experience in substrate design and package to board integration

Good understanding of manufacturability, interconnect technologies, and package reliability

Proven ability to work across multidisciplinary engineering and external partner teams

Strong technical judgement, communication, and problem solving skills

Degree in a relevant engineering or physical sciences discipline

Experience with AI accelerators, high performance compute, networking, or advanced data centre hardware

Familiarity with wafer level packaging

Experience mentoring engineers

Familiarity with package reliability, qualification, and failure analysis workflows

Exposure to new product introduction and scaling advanced package technologies into production

Competitive Salary: Commensurate with your experience, skills, and location

Equity & Ownership: Meaningful stock options. You're not just joining the mission; you're owning a piece of it

Proximity Bonus: We value your time. To minimise your commute and maximise your life, we offer an annual Living Local Bonus if your residence is within 20 minutes of the office

Retirement Benefits:Employer contributed retirement plans to help you build long term financial security.

Due to U.S. export control regulations, candidates' eligibility to work at OLIX depends on their most recent citizenship or permanent residency status. We are generally unable to consider applicants whose most recent citizenship or permanent residence is in certain restricted countries (currently including Iran, North Korea, Syria, Cuba, Russia, Belarus, China, Hong Kong, Macau, and Venezuela). Applicants who have subsequently obtained citizenship or permanent residency in another country not subject to these restrictions may still be eligible.

We do not accept unsolicited CVs from recruitment agencies, will not be liable for any fees, and prohibit unauthorised use of our company name in recruitment activities.