Senior FPGA Engineer - RTL Design, Verification & Bring-up (Relocation/Visa)

Plessey in Oxford is seeking a Senior FPGA Engineer to architect, design, implement and verify FPGA RTL for high-speed digital, video, and optical-interfacing systems. You will own the FPGA design end-to-end and define RTL standards for others to follow.

You will collaborate with electronics, RF, and photonics teams to bring prototypes toward product. The role emphasizes architecture, RTL design, verification, and timing closure across multiple clock domains.