Senior Design Verification Engineer - SoC & IP (UVM/Formal)

A leading global semiconductor company is seeking a Staff Engineer, Design Verification in Edinburgh. The role involves verifying complex designs, developing verification methodologies, and mentoring junior engineers. Ideal candidates will have a Bachelor's or Master's degree in Engineering and 5-10 years of experience in ASIC design verification. The position requires strong knowledge of System Verilog, UVM, debugging skills, and proficiency in scripting languages. Successful candidates will join a collaborative team focused on advanced semiconductor solutions.