Senior ASIC Verification Lead for DDR/PCIe IP

Synopsys, Inc. is seeking an experienced ASIC Digital Verification Engineer to design and implement verification environments for Interface IP protocols and to drive coverage closure.

You will collaborate with design teams to identify and fix issues, develop VIP and testbenches, and mentor junior engineers to uphold high standards of quality. You should have deep expertise in SystemVerilog/UVM and be comfortable validating DDR, PCIe, CXL, and Ethernet interfaces across complex ASIC designs.