Senior ASIC Verification Engineer - DDR/PCIe IP Lead

Synopsys, Inc. is seeking an experienced ASIC Digital Verification Engineer to design and implement verification environments for Interface IP protocols. You will develop verification IP and testbenches using SystemVerilog and UVM, and collaborate with design teams to fix bugs while driving coverage closure.

You will mentor junior engineers and contribute to high-quality ASIC designs that power a range of semiconductor technologies.