Senior ASIC Mid-End Engineer - AI-Driven Flows & Automation

Synopsys is seeking a Senior EDA Engineer for its HPC Controller IP mid-end team in Dublin. You will drive mid-end flows, automate synthesis, and collaborate with RTL, verification, DFT, and physical-design teams to ensure clean, implementation-ready inputs.

You will apply AI to accelerate debugging, triage flow logs, and summarize QoR trends while advancing flow robustness and documentation quality. A strong background in ASIC design and formal checks is required.