Principal Analog Layout Architect (65nm+)

A semiconductor company in the United Kingdom is seeking a Principal Analog Layout Engineer with a minimum of 5 years experience, ideally over 8 years. The role demands expertise in analog layout for 65nm and below, particularly focusing on critical timing layouts and matching techniques for timing circuits. Experience with Cadence tools and chip finishing is a bonus. This position offers a unique opportunity for professionals looking to contribute to cutting-edge projects in a dynamic environment.