Mixed-Signal Verification Engineer (SerDes/DDR/PLL)

QUALCOMM Cork is seeking Mixed-Signal Design Verification Engineers to verify SerDes, DDR and PLL IP as part of the MSIP group. Work with analog and digital teams across architecture, design and software to integrate IP into Snapdragon products in 3nm and below nodes.

You will perform SV/UVM based verification, develop test benches, and drive pre/post-silicon validation with cross-functional teams in Cork, Ireland. Excellent communication and collaboration are essential.