AMS Layout with finFET experience

Overview

AMS LAYOUT ENGINEERS WITH FINFET EXPERIENCE

Responsibilities

• The Layout Engineer will work closely with circuit designers. The layouts are for analog and mixed signal circuits, high speed SerDes I/O, PLLs and ESD structures.
• Chip planning and block implementation.
• Ability to plan and estimate layout schedules.
• Ability to work with designers and good communication skills.

Qualifications

• Previous experience doing analog matching requirements is essential.
• Experience working on various analog IP blocks including PLLs, ADC, DAC, Bandgap reference and other high speed connectivity circuits.
• Solid understanding of parasitic RC delay, signal integrity and EM Deep sub-micron CMOS layout experience 16nm and smaller geometries.
• Previous exposure to 10nm, 7nm, or 5nm would be a big advantage.
• Previous experience using Cadence virtuoso tool.
• Familiarity of layout techniques for device matching, minimize parasitic, high speed routing.
• Knowledge of layout extractions, verification methods including LVS, DRC and ERC checks.

Senior Analog & AMS Recruitment Specialist