Senior Digital IC Design Engineer

Job Title: Senior Digital IC Design Engineer

Position: Permanent

Location: Cambridge

Salary Range: DOE

Client Information: Semiconductor company specializing in high-performance electronic components for high-voltage power conversion systems. Their innovative integrated circuits and diodes enable compact, energy-efficient AC-DC power supplies used across a wide range of products, from mobile devices, TVs, and computers to home appliances, smart meters, and LED lighting.

Responsibilities

• Demonstrate in-depth knowledge and understanding of best-practice digital design methodologies.
• Execute designs using a fully synthesized digital design flow, including RTL design and logic synthesis.
• Be fully conversant with the SystemVerilog standard and scripting languages such as TCL.
• Apply design constraints and utilize automatic place-and-route flows for physical implementation.
• Understand the importance of production testing and apply design methods to maximize test coverage (e.g., scan insertion).
• Employ design techniques aimed at optimizing digital power consumption.
• Debug digital functions in a laboratory environment using appropriate test equipment (e.g., mixed-signal oscilloscopes).
• Produce accurate, clear, and comprehensive design documentation.

Requirements

• Develop functional digital blocks and contribute to complete mixed-signal ASICs from initial definition through to full production maturity.
• Collaborate with the Product Definition team on feasibility studies, product architecture definition, and digital block design for FPGA emulation.
• Perform RTL design in SystemVerilog for digital functions, ensuring all specification requirements are fully met.
• Create block-level test benches to enable comprehensive verification of all digital blocks.
• Develop behavioural models and top-level test benches for complete verification and regression testing of system-level and production test functions.
• Carry out digital synthesis with appropriate physical constraints to achieve power, performance, and area (PPA) targets.
• Define and implement DFT architectures, performing scan insertion, ATPG, and adding test points to meet required test coverage levels.
• Define the digital layout floorplan, oversee place-and-route activities, and ensure successful post-layout timing closure.
• Prepare detailed design documentation and actively participate in design and peer reviews.
• Contribute to product-level verification and validation planning.
• Support silicon evaluation, product validation, and bring-up activities in collaboration with Product, Quality, and Test Engineering teams through to production ramp-up.
• Drive continuous improvements in technology processes and digital design methodologies.

Contact

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